1. Field of the Invention
The present invention provides a NAND flash memory system, and more particularly, a NAND flash memory system with programmable connections between a NAND flash memory controller and a plurality of NAND flash memory modules.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a conventional single channel NAND flash memory system 100. The conventional single channel NAND flash memory system 100 comprises a NAND flash memory controller 110 and a NAND flash memory module M1. The NAND flash memory controller 110 comprises a data interface 111, an action control interface 112, a chip enable interface 113, and a status interface 114. The NAND flash memory module M1 comprises a data interface M11, an action control interface M12, a chip enable interface M13, and a status interface M14.
The data interface 111 of the NAND flash memory controller 110 comprises 2 8-bit data ports D1 and D2. M11 is coupled to the data interface 111 through the port D1 for exchanging data with the NAND flash controller 110 so that a data with 8-bit data width is transmitted between the NAND flash memory controller 110 and the NAND flash memory modules M1. It is assumed that a single channel NAND flash memory system is defined by the data width and here we define a single channel NAND flash memory system with an 8-bit data width.
The action control interface 112 comprises 2 action control ports AC1 and AC2. The action control interface 112 is coupled to the action control interfaces M12 through the port AC1 for transmitting action control signals to the NAND flash memory module M1. The action control signals control the actions of the NAND flash memory modules M1.
The chip enable interface 113 comprises 4 chip enable ports CE1, CE2, CE3, and CE4. The chip enable interface 113 is coupled to the chip enable interface M13 through port CE1 for transmitting chip enable signals to the NAND flash memory module M1. For example, if the chip enable interface 113 transmits a chip enable signal to the chip enable interface M13 of the NAND flash memory module M1 through the port CE1, then the NAND flash memory module M1 is enabled to execute corresponding actions according to the action control signals.
The status interface 114 comprises 2 status ports RB1 and RB2. The status interface 114 is coupled to the status interfaces M14 through port RB1 for receiving status signals from the NAND flash memory modules M1. For example, if the NAND flash memory module M1 is busy, the NAND flash memory module M1 transmits a busy signal to the status interface 114 through the port RB1, then the controller 110 can know the NAND flash memory module M1 is busy and stops the following actions until the NAND flash memory module M1 is ready. Therefore, for example, if the NAND flash memory controller 110 is about to write data to the NAND flash memory module M1, the NAND flash memory controller 110 checks if the NAND flash memory module M1 is ready through the port RB1 of the status interface 114. If yes, the NAND flash memory controller 110 transmits a chip enable signal to the chip enable interface M13 of the NAND flash memory module M1 through the port CE1 of the chip enable interface 113 to enable the NAND flash memory module M1, transmits a write action and address to the NAND flash memory module M1 through the action control interface 112 and data interface 111, transmits the data to the NAND flash memory module M1 through the data interface 111, transmits a write confirm action to the NAND flash memory module M1 through the action control interface 112 and data interface 111. Then, the data is written into the NAND flash memory module M1.
In NAND flash memory system 100, the total density of the NAND flash memory system is equal to the density of NAND flash memory M1, that is, if the size of a NAND flash memory M1 is 1 MB, the total density of the NAND flash memory system is 1 MB.
Please refer to FIG. 2. FIG. 2 is a diagram illustrating another single-channel NAND flash memory system 200. The single-channel NAND flash memory system 200 is an expansion of the single-channel NAND flash memory system 100 illustrated in FIG. 1. The single channel NAND flash memory system 200 comprises a NAND flash memory controller 110 and 4 NAND flash memory modules M2-M5. The NAND flash memory modules M2-M5 are the same as the NAND flash memory module M1. Thus, the total density is 4 MB if the density of a NAND flash memory is 1 MB.
In NAND flash memory system 200, the chip enable interface 113 is respectively coupled to the chip enable interface M23, M33, M43, and M53 through ports CE1, CE2, CE3, and CE4 for respectively transmitting chip enable signals to the NAND flash memory modules M2-M5. For example, if the chip enable interface 113 transmits a chip enable signal to the chip enable interface M23 of the NAND flash memory module M2 through the port CE1, then the NAND flash memory module M2 is enabled to occupy the data bus coupled to the data interface 111 of the NAND flash controller 110 and execute corresponding actions according to the action control signals.
The status interface of each NAND flash memory modules M24, M34, M44 and M54 are conjointly coupled to the status interface 114 through the port RB1. In this way, as long as any of the NAND flash memory modules M2-M5 is busy, the NAND flash memory controller 110 considers all the NAND flash memory modules M2-M5 are busy and halts the related action. The related action is not continued until all the NAND flash memory modules M2 to M5 are ready. Therefore, for example, if the NAND flash memory controller 110 is about to write data to the NAND flash memory module M2, the NAND flash memory controller 110 checks if NAND flash memories M2 is ready through the port RB1 of the status interface 114. If yes, the NAND flash memory controller 110 transmits a chip enable signal to the chip enable interface M23 of the NAND flash memory module M2 through the port CE1 of the chip enable interface 113 to enable the NAND flash memory module M2, transmits write action and address to the NAND flash memory module M2 through the action control interface 112 and data interface 111, transmits the data to the NAND flash memory module M2 through the data interface 111, transmits a write confirm action to the NAND flash memory module M2 through the action control interface 112 and data interface 111. Then, the data is written into the NAND flash memory module M2.
Please continue referring to FIG. 2. The drawback of the single channel NAND flash memory system 200 is that the NAND flash memory controller 110 is not flexible to control the NAND flash memory modules M2-M5 especially when any of the NAND flash memory modules M2-M5 is dead.
For example, if the NAND flash memory module M2 is dead the NAND flash memory controller 110 still writes data to the NAND flash memory module M2 so that the written data is not stored in the NAND flash memory module M2. Thus, when the NAND flash memory controller 110 is about to read the written data stored in the NAND flash memory module M2, the NAND flash memory controller 110 reads a wrong data or nothing. There are still 3 NAND flash memory modules M3-M5 active, that is, if the size of a NAND flash memory module is 1 MB, there are still 3 MB memories available. But due to the inflexibility of the controller 110, the conventional single channel NAND flash memory system 200 does not work and the available 3 MB NAND flash memory modules are wasted.
Please refer to FIG. 3. FIG. 3 is a diagram illustrating a conventional dual channel NAND flash memory system 300. The conventional dual channel NAND flash memory system 300 comprises a NAND flash memory controller 110 and 2 NAND flash memory modules M6 and M7. The NAND flash memory modules M6 and M7 are the same as the NAND flash memory module M1.
The data interface 111 is respectively coupled to the data interfaces M61 and M71 through the ports D1 and D2 for exchanging data with the NAND flash memory modules M6 and M7. Generally, the ports D1 and D2 are both 8-bit data port, and each data interface of the NAND flash memory modules M6 and M7 has an 8-bit data port as well. The system 300 is named as “dual channel” because the data ports of the NAND flash memory modules M6 and M7 are coupled to the different data port of the data interface 111 so that a data with doubled 8-bit data width is transmitted between the NAND flash memory controller 110 and the NAND flash memory modules M6 and M7. It is assumed that a dual channel NAND flash memory system is defined by the data width instead of the amount of the NAND flash memory modules and here we define a dual channel NAND flash memory system with a doubled 8-bit data width. Thus, the amount of the NAND flash memory modules of a dual channel NAND flash memory system can be any number and does not have to be 2.
The action control interface 112 is respectively coupled to the action control interfaces M62 and M72 through ports AC1 and AC2 for transmitting action control signals to the NAND flash memory modules M6 and M7.
The chip enable interface 113 is conjointly coupled to the chip enable interface M63 and M73 for transmitting chip enable signals to the NAND flash memory modules M6 and M7. Thus, if the chip enable interface 113 transmits a chip enable signal through the port CE1, then the NAND flash memory modules M6 and M7 are both enabled to execute corresponding actions according to the action control signals.
The status interface 114 is respectively coupled to the status interfaces M64 and M74 through ports RB1 and RB2 for respectively receiving status signals from the NAND flash memory modules M6 and M7. Thus, if the NAND flash memory module M6 is busy, the NAND flash memory module M6 transmits a busy signal to the status interface 114 through the port RB1, then the controller 110 can know the NAND flash memory module M6 is busy and stops the following actions until the NAND flash memory module M6 is ready. Therefore, for example, if the NAND flash memory controller 110 is about to write data to the NAND flash memory module M6, the NAND flash memory controller 110 checks if the NAND flash memory modules M6 is ready through the ports RB1 of the status interface 114. If yes, the NAND flash memory controller 110 transmits a chip enable signal to enable the NAND flash memory modules M6, transmits write action and address to the NAND flash memory module M6 through the action control interface 112 and data interface 111, transmits the data to the NAND flash memory module M6 through the data interface 111, transmits a write confirm action to the NAND flash memory module M6 through the action control interface 112 and data interface 111. Then, the data is written into the NAND flash memory module M6.
Please refer to FIG. 3. The drawback of the conventional dual channel NAND flash memory system 300 is that the NAND flash memory controller 110 is not flexible to control the NAND flash memory modules M6 and M7 when M6 is dead.
For example, if M7 is dead, the NAND flash memory system can still work like a single NAND flash memory system 100 shown in FIG. 1. However, if the NAND flash memory module M6 is dead, the NAND flash memory system can't work like a single NAND flash memory system 100 because all the signals of the NAND flash controller 110 are coupled to M7 through the second ports of the interfaces such as D2, AC2, RB2. In the case, there are still 1 NAND flash memory module active, that is, if the size of a NAND flash memory module is 1 MB, there are still 1 MB memories available. But due to the inflexibility of the controller, the conventional dual-channel NAND flash memory system 300 does not work and the available 1 MB NAND flash memory modules are wasted.
Please refer to FIG. 4. FIG. 4 is a diagram illustrating another conventional dual channel NAND flash memory system 400. The NAND flash memory system 400 comprises a NAND flash memory controller 110 and 2 NAND flash memory modules M8 and M9. The NAND flash memory modules M8 and M9 are the same as the NAND flash memory module M1. In the NAND flash memory system 400, the action control interface 112 is coupled to the action control interfaces M82 and M92. And the status interfaces M84 and M94 are conjointly coupled to the status interface 114.
Please refer to FIG. 5. FIG. 5 is a diagram illustrating another dual channel NAND flash memory system 500. The NAND flash memory system 500 is an expansion of NAND flash memory system 300 shown in FIG. 3. The NAND flash memory system 500 comprises a NAND flash memory controller 110 and 4 identical NAND flash memory modules MA-MD. The NAND flash memory modules MA-MD are the same as the NAND flash memory module M1. Thus, the total density is 4 MB and the density of a NAND flash memory is 1 MB.
In NAND flash memory system( 500, the chip enable interface 113 is respectively coupled to the chip enable interfaces MA3, MB3, MC3, and MD3 through the ports CE1, CE2, CE1 and CE2. Thus, if the chip enable interface 113 transmits a chip enable signal to the chip enable interface MA3 and MC3 through the port CE1, then the NAND flash memory module MA and MC are enabled to execute corresponding actions according to the action control signals.
The status interface of NAND flash memory module MA4 and MB4 are conjointly coupled to the status interface 114 through the port RB1. And the status interface of NAND flash memory module MC4 and MD4 are conjointly coupled to the status interface 114 through the port RB2. Thus, if the NAND flash memory controller 110 is about to write data to the NAND flash memory module MA, the NAND flash memory controller 110 checks if the NAND flash memories MA is ready through the port RB1 of the status interface 114. If yes, the NAND flash memory controller 110 transmits a chip enable signal to the chip enable interface MA3 of the NAND flash memory module MA through the port CE1 of the chip enable interface 113 to enable the NAND flash memory module MA, transmits write action and address to the NAND flash memory module MA through the action control interface 112 and data interface 111, transmits the data to the NAND flash memory module MA through the data interface 111, transmits a write confirm action to the NAND flash memory module MA through the action control interface 112 and data interface 111. Then, the data is written into the NAND flash memory module MA.